Silicon technology now allows us to build chips consisting of tens of millions of transistors. This technology promises new levels of system integration onto a single chip, but also presents significant challenges to the chip designer. As a result, many ASIC developers and silicon vendors are re-examining their design methodologies, searching for ways to make effective use of the huge numbers of gates now available. These designers see current design tools and methodologies as inadequate for developing million-gate ASICs from scratch. There is considerable pressure to keep design team size and design schedules constant while design complexities grow. Tools are not providing the productivity gains required to keep pace with the increasing gate counts available from deep submicron technology. Design reuse - the use of pre-designed and pre-verified cores - is the most promising opportunity to bridge the gap between available gate-count and designer productivity. Reuse Methodology Manual for System-On-A-Chip Designs outlines an effective methodology for creating reusable designs for use in a System-on-a-Chip (SoC) design methodology. Silicon and tool technologies move so quickly that no single methodology can provide a permanent solution to this highly dynamic problem. Instead, this manual is an attempt to capture and incrementally improve on current best practices in the industry, and to give a coherent, integrated view of the design process. From the Foreword `Synopsys and Mentor Graphics have joined forces to help make IP reuse a reality. One of the goals of our Design Reuse Partnership is to develop, demonstrate, and document a reuse-based design methodology that works. The Reuse Manual (RMM) is the result of this effort.' Aart J. de Geus, Synopsys, Inc. Walden C. Rhines, Mentor Graphics Corporation

Reuse Methodology Manual for System-On-A-Chip Designs

Computers & Technology

Keating, Michael

Graphics & Design

KLUWER ACADEMIC@PUBLISHERS

The last decade has seen an explosion in integrated circuit technology. Improved manufacturing processes have led to ever smaller device sizes. Chips with over a hundred thousand transistors have become common and performance has improved dramatically. Alongside this explosion in manufacturing technology has been a much-less-heralded explosion of design tool capability that has enabled designers to build those large, complex devices. The tools have allowed designers to build chips in less time, reducing the cost and risk. Without the design tools, we would not now be seeing the full benefits of the advanced manufacturing technology. The Scope of This Book This book describes the implementation of several tools that are commonly used to design integrated circuits. The tools are the most common ones used for computer aided design and represent the mainstay of design tools in use in the industry today. This book describes proven techniques. It is not a survey of the newest and most exotic design tools, but rather an introduction to the most common, most heavily-used tools. It does not describe how to use computer aided design tools, but rather how to write them. It is a view behind the screen, describing data structures, algorithms and code organization. This book covers a broad range of design tools for Computer Aided Design (CAD) and Computer Aided Engineering (CAE). The focus of the discussion is on tools for transistor-level physical design and analysis.

An Introduction to CAD for VLSI

Engineering & Transportation

Trimberger, Stephen

Engineering

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