A Vhdl Primer

An introduction to VHDL, clarifying the language by presenting a subset of VHDL so readers can quickly start writing models. It presents the most common usage instead of describing the complete syntax of language constructs. Describing the basic elements of the language, the author includes a quick tutorial to demonstrate the primary modelling features. It also provides illustrative examples that explain the different formulations of the language constructs and their semantics.