Adaptive filtering is commonly used in many communication applications including speech and video predictive coding, mobile radio, ISDN subscriber loops, and multimedia systems. Existing adaptive filtering topologies are non-concurrent and cannot be pipelined. Pipelined Adaptive Digital Filters presents new pipelined topologies which are useful in reducing area and power and in increasing speed. If the adaptive filter portion of a system suffers from a power-speed-area bottleneck, a solution is provided. Pipelined Adaptive Digital Filters is required reading for all users of adaptive digital filtering algorithms. Algorithm, application and integrated circuit chip designers can learn how their algorithms can be tailored and implemented with lower area and power consumption and with higher speed. The relaxed look-ahead techniques are used to design families of new topologies for many adaptive filtering applications including least mean square and lattice adaptive filters, adaptive differential pulse code modulation coders, adaptive differential vector quantizers, adaptive decision feedback equalizers and adaptive Kalman filters. Those who use adaptive filtering in communications, signal and image processing algorithms can learn the basis of relaxed look-ahead pipelining and can use their own relaxations to design pipelined topologies suitable for their applications. Pipelined Adaptive Digital Filters is especially useful to designers of communications, speech, and video applications who deal with adaptive filtering, those involved with design of modems, wireless systems, subscriber loops, beam formers, and system identification applications. This book can also be used as a text for advanced courses on the topic.

Pipelined Adaptive Digital Filters (The Springer International Series in Engineering and Computer Science, 274)

Computers & Technology

Shanbhag, Naresh R.

Parhi, Keshab K.

Computer Science

Springer

Deep In-memory Architectures for Machine Learning

This book describes the recent innovation of deep in-memory architectures for realizing AI systems that operate at the edge of energy-latency-accuracy trade-offs. From first principles to lab prototypes, this book provides a comprehensive view of this emerging topic for both the practicing engineer in industry and the researcher in academia. The book is a journey into the exciting world of AI systems in hardware.

Kang, Mingu

Gonugondla, Sujan

Reference

This book describes the recent innovation of deep in-memory architectures for realizing AI systems that operate at the edge of energy-latency-accuracy trade-offs. From first principles to lab prototypes, this book provides a comprehensive view of this emerging topic for both the practicing engineer in industry and the researcher in academia. The book is a journey into the exciting world of AI systems in hardware.\nFrom the Back Cover\nThis book describes the recent innovation of deep in-memory architectures for realizing AI systems that operate at the edge of energy-latency-accuracy trade-offs. From first principles to lab prototypes, this book provides a comprehensive view of this emerging topic for both the practicing engineer in industry and the researcher in academia. The book is a journey into the exciting world of AI systems in hardware.\nDescribes deep in-memory architectures for AI systems from first principles, covering both circuit design and architectures; Discusses how DIMAs pushes the limits of energy-delay product of decision-making machines via its intrinsic energy-SNR trade-off; Offers readers a unique Shannon-inspired perspective to understand the system-level energy-accuracy trade-off and robustness in such architectures; Illustrates principles and design methods via case studies of actual integrated circuit prototypes with measured results in the laboratory; Presents DIMA's various models to evaluate DIMA's decision-making accuracy, energy, and latency trade-offs with various design parameter.

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Books by Shanbhag, Naresh R.