Timing Analysis and Optimization of Sequential Circuits

Recent years have seen rapid strides in the level of sophistication of VLSI circuits. On the performance front, there is a vital need for techniques to design fast, low-power chips with minimum area for increasingly complex systems, while on the economic side there is the vastly increased pressure of time-to-market. These pressures have made the use of CAD tools mandatory in designing complex systems. Timing Analysis and Optimization of Sequential Circuits describes CAD algorithms for analyzing and optimizing the timing behavior of sequential circuits with special reference to performance parameters such as power and area. A unified approach to performance analysis and optimization of sequential circuits is presented. The state of the art in timing analysis and optimization techniques is described for circuits using edge-triggered or level-sensitive memory elements. Specific emphasis is placed on two methods that are true sequential timing optimizations techniques: retiming and clock skew optimization. Timing Analysis and Optimization of Sequential Circuits covers the following topics: 
<ul>
<li>Algorithms for sequential timing analysis </li> <li>Fast algorithms for clock skew optimization and their applications </li> <li>Efficient techniques for retiming large sequential circuits </li> <li>Coupling sequential and combinational optimizations. </li> </ul>
 Timing Analysis and Optimization of Sequential Circuits is written for graduate students, researchers and professionals in the area of CAD for VLSI and VLSI circuit design.

Computers & Technology

Sapatnekar, S.

Maheshwari, Naresh

Programming

Springer

Moore's law [Noy77], which predicted that the number of devices in tegrated on a chip would be doubled every two years, was accurate for a number of years. Only recently has the level of integration be gun to slow down somewhat due to the physical limits of integration technology. Advances in silicon technology have allowed Ie design ers to integrate more than a few million transistors on a chip; even a whole system of moderate complexity can now be implemented on a single chip. To keep pace with the increasing complexity in very large scale integrated (VLSI) circuits, the productivity of chip designers would have to increase at the same rate as the level of integration. Without such an increase in productivity, the design of complex systems might not be achievable within a reasonable time-frame. The rapidly increasing complexity of VLSI circuits has made de- 1 2 INTRODUCTION sign automation an absolute necessity, since the required increase in productivity can only be accomplished with the use of sophisticated design tools. Such tools also enable designers to perform trade-off analyses of different logic implementations and to make well-informed design decisions.

Design Automation for Timing-Driven Layout Synthesis (The Springer International Series in Engineering and Computer Science, 198)

Sung-Mo (Steve) Kang

Recent years have seen rapid strides in the level of  sophistication of VLSI circuits. On the performance front, there is a  vital need for techniques to design fast, low-power chips with minimum  area for increasingly complex systems, while on the economic side  there is the vastly increased pressure of time-to-market. These  pressures have made the use of CAD tools mandatory in designing  complex systems.   Timing Analysis and Optimization of Sequential Circuits  describes CAD algorithms for analyzing and optimizing the timing  behavior of sequential circuits with special reference to performance  parameters such as power and area. A unified approach to performance  analysis and optimization of sequential circuits is presented. The  state of the art in timing analysis and optimization techniques is  described for circuits using edge-triggered or level-sensitive memory  elements. Specific emphasis is placed on two methods that are true  sequential timing optimizations techniques: retiming and clock skew  optimization.   Timing Analysis and Optimization of Sequential Circuits covers  the following topics:  Algorithms for sequential  timing analysis   Fast algorithms for clock skew optimization and  their applications   Efficient techniques for retiming large  sequential circuits   Coupling sequential and combinational  optimizations.        Timing Analysis and Optimization of Sequential Circuits is  written for graduate students, researchers and professionals in the  area of CAD for VLSI and VLSI circuit design.

See the best price to sell, buy, or rent books by Sapatnekar, S.. BookScouter helps to compare book prices from 25+ online bookstores and 30+ buyback vendors with a single search.

Books by Sapatnekar, S.

See the best price to sell, buy, or rent books by Sapatnekar, S.. BookScouter helps to compare book prices from 25+ online bookstores and 30+ buyback vendors with a single search.

Timing Analysis and Optimization of Sequential Circuits

Design Automation for Timing-Driven Layout Synthesis (The Springer International Series in Engineering and Computer Science, 198)

Timing Analysis and Optimization of Sequential Circuits