Verification by Error Modeling: Using Testing Techniques in Hardware Verification (Frontiers in Electronic Testing)

<p>This book presents the basis for reusing the test vector generation and simulation for the purpose of implementation verification, to result in a significant timesaving. It brings the results in the direction of merging manufacturing test vector generation and verification. </p>

Verification by Error Modeling: Using Testing Techniques in Hardware Verification (Frontiers in Electronic Testing, 25)

Computers & Technology

Radecka, Katarzyna

Zilic, Zeljko

Computer Science

Springer

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Books by Radecka, Katarzyna

See the best price to sell, buy, or rent books by Radecka, Katarzyna. BookScouter helps to compare book prices from 25+ online bookstores and 30+ buyback vendors with a single search.

Verification by Error Modeling: Using Testing Techniques in Hardware Verification (Frontiers in Electronic Testing, 25)

Verification by Error Modeling: Using Testing Techniques in Hardware Verification (Frontiers in Electronic Testing)