Surveys the latest research and field-proven techniques for every form of memory fault tolerance, including manufacturing, online, and field-related fault tolerance. Authors focus on practical circuit and design solutions.

Fault-Tolerance and Reliability Techniques for High-Density Random-Access Memories (Prentice Hall Modern Semiconductor Design Series)

Computers & Technology

Mazumder, Pinaki

Chakraborty, Kanad

Computer Science

PRENTICE/HALL

Genetic algorithms mimic the natural process of evolution, helping engineers optimize their designs by using the principle of 'survival of the fittest.' VLSI is especially suited to benefit from genetic algorithms - and this comprehensive book shows you how to get the best results, fast. Youll discover how genetic algorithms work and how you can use them in a wide variety of VLSI design, layout, and test automation tasks, including: Circuit partitioning Macro cell routing, including Steiner problems and global routing Standard cell and macro cell placement Circuit segmentation, FPGA mapping and pseudo-exhaustive testing Automatic test generation including compaction, eterministic/genetic test hybrids and integration of finite state machine sequences Peak power estimation Youll find essential insights into problem encoding and fitness functions; coverage of advanced parallel implementations; and much more. Specific experimental results are presented for every application - as are detailed problem descriptions and easy-to-adapt examples. Genetic algorithms are already being incorporated into leading electronic design automation systems. Leverage their full power now - with Genetic Al

Genetic Algorithms for Vlsi Design, Layout & Test Automation

Rudnick, Elizabeth M.

Programming

Explains current co-design and co-optimization methodologies for building hardware neural networks and algorithms for machine learning applications This book focuses on how to build energy-efficient hardware for neural networks with learning capabilities―and provides co-design and co-optimization methodologies for building hardware neural networks that can learn. Presenting a complete picture from high-level algorithm to low-level implementation details, Learning in Energy-Efficient Neuromorphic Computing: Algorithm and Architecture Co-Design also covers many fundamentals and essentials in neural networks (e.g., deep learning), as well as hardware implementation of neural networks. The book begins with an overview of neural networks. It then discusses algorithms for utilizing and training rate-based artificial neural networks. Next comes an introduction to various options for executing neural networks, ranging from general-purpose processors to specialized hardware, from digital accelerator to analog accelerator. A design example on building energy-efficient accelerator for adaptive dynamic programming with neural networks is also presented. An examination of fundamental concepts and popular learning algorithms for spiking neural networks follows that, along with a look at the hardware for spiking neural networks. Then comes a chapter offering readers three design examples (two of which are based on conventional CMOS, and one on emerging nanotechnology) to implement the learning algorithm found in the previous chapter. The book concludes with an outlook on the future of neural network hardware. <ul>
<li>Includes cross-layer survey of hardware accelerators for neuromorphic algorithms</li> <li>Covers the co-design of architecture and algorithms with emerging devices for much-improved computing efficiency</li> <li>Focuses on the co-design of algorithms and hardware, which is especially critical for using emerging devices, such as traditional memristors or diffusive memristors, for neuromorphic computing</li> </ul>
Learning in Energy-Efficient Neuromorphic Computing: Algorithm and Architecture Co-Design is an ideal resource for researchers, scientists, software engineers, and hardware engineers dealing with the ever-increasing requirement on power consumption and response time. It is also excellent for teaching and training undergraduate and graduate students about the latest generation neural networks with powerful learning capabilities.

Learning in Energy-Efficient Neuromorphic Computing: Algorithm and Architecture Co-Design (IEEE Press)

Zheng, Nan

Wiley-IEEE Press

VLSI Interconnect Technology with Artificial Plasmonics: Bridging the Gap between Electronics and Optics

Engineering & Transportation

Joy, Soumitra R.

Engineering

Testing and Testable Design of High-Density Random-Access Memories (Frontiers in Electronic Testing)

Testing and Testable Design of High-Density Random-Access Memories deals with the study of fault modeling, testing and testable design of semiconductor random-access memories. It is written primarily for the practising design engineer and the manufacturer of random-access memories (RAMs) of the modern age. It provides useful exposure to state-of-the-art testing schemes and testable design approaches for RAMs. It is also useful as a supplementary text for undergraduate courses on testing and testability of RAMs. Testing and Testable Design of High-Density Random-Access Memories presents an integrated approach to state-of-the-art testing and testable design techniques for RAMs. These new techniques are being used for increasing the memory testability and for lowering the cost of test equipment. Semiconductor memories are an essential component of digital computers - they are used as primary storage devices. They are used in almost all home electronic equipment, in hospitals and for avionics and space applications. From hand-held electronic calculators to supercomputers, we have seen generations of memories that have progressively become smaller, smarter and cheaper. For the past two decades there has been vigorous research in semiconductor memory design and testing. Such research has resulted in bringing the dynamic RAM (DRAM) to the forefront of the microelectronics industry in terms of achievable integration levels, high performance, high reliability, low power and low cost. The DRAM is regarded as the technological driver for the commercial microelectronics industry. Testing and Testable Design of High-Density Random-Access Memories deals with real- world examples that will be useful to readers. This book also provides college and university students with a systematic exposure to a wide spectrum of issues related to RAM testing and testable design.

Springer

Nanoscale devices attracted significant research effort from the industry and academia due to their operation principals being based on different physical properties which provide advantages in the design of certain classes of circuits over conventional CMOS transistors. Neuromorphic Circuits for Nanoscale Devices contains recent research papers presented in various international conferences and journals to provide insight into how the operational principles of the nanoscale devices can be utilized for the design of neuromorphic circuits for various applications of non-volatile memory, neural network training/learning, and image processing. The topics discussed in the book include: 
<ul>
<li>Nanoscale Crossbar Memory Design</li>
<li>Q-Learning and Value Iteration using Nanoscale Devices</li>
<li>Image Processing and Computer Vision Applications for Nanoscale Devices</li>
<li>Nanoscale Devices-based Cellular Nonlinear/Neural Networks</li>
</ul>

Neuromorphic Circuits for Nanoscale Devices (River Publishers Series in Biomedical Engineering)

Yilmaz, Yalcin

Ebong, Idongesit

River Publishers

Lectures on Digital Design Principles (River Publishers Series in Electronic Materials, Circuits and Devices)

Ebong, Idongesit E.

Memristive Computing

Nyima Tashi

Feng, Xiao

Yu, Yongbin

Wang, Xiangxiang

Shen, Jiarun

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