A selection of 14 of the 19 papers presented at the workshop cover measuring, understanding, and optimizing application and system performance; prediction and speculative execution; interactions between hardware and software in architecture design; compilation; and parallel system architecture. Specific topics include system support for the dynamic optimization of application performance, a speculative multi-threading with selective multi-path execution, new methods for exploiting program structure and behavior in computer architecture, implementing a non-strict functional programming language V on a threaded architecture EARTH, and the architecture of a parallel computer Cenju-4. Only authors are indexed. Annotation c. Book News, Inc., Portland, OR (booknews.com)

Innovative Architecture for Future Generation High-Performance Processors and Systems

Computers & Technology

Maui High-Performance Computing Center

International Workshop on Innovative Architecture

Hardware & DIY

IEEE Computer Society

Contains 11 papers presented at the November 1999 workshop that discussed computer architecture, compilers, and applications for high- performance systems. Some of the topics are near fine grain parallel processing using static scheduling on single ship multiprocessors, PIM architectures to support

Innovative Architecture for Future Generation High-Performance Processors and Systems: 1999 International Workshop on Innovative Architectures (Iwia '99) November 1-3, 1999 Maui, Hawaii

National Science Foundation (U. S.)

International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (2001 : Maui, Hawaii)

IEEE

Innovative Architecture for Future Generation High-Performance Processors and Systems: 18-19 January 2001 Maui, Hawaii

Science & Math

Veidenbaum, Alex

Joe, Kazuki

DARPA/ITO PAC/C Program

Mathematics

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